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ATmega128
Figure 64. Compare Match Output Unit, Schematic
COMn1
COMn0
FOCn
Waveform
Generator
D
Q
1
OCn
OCn
D
Q
PORT
D
Q
0
Pin
DDR
clk I/O
The general I/O port function is overridden by the output compare (OC2) from the waveform
generator if either of the COM21:0 bits are set. However, the OC2 pin direction (input or output)
is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Regis-
ter bit for the OC2 pin (DDR_OC2) must be set as output before the OC2 value is visible on the
pin. The port override function is independent of the W aveform Generation mode.
The design of the output compare pin logic allows initialization of the OC2 state before the out-
put is enabled. Note that some COM21:0 bit settings are reserved for certain modes of
operation. See “8-bit Timer/Counter Register Description” on page 156.
Compare Output Mode
and Waveform
Generation
Modes of
Operation
Normal Mode
The waveform generator uses the COM21:0 bits differently in normal, CTC, and P W M modes.
For all modes, setting the COM21:0 = 0 tells the waveform generator that no action on the OC2
Register is to be performed on the next compare match. For compare output actions in the non-
P W M modes refer to Table 65 on page 157 . For fast P W M mode, refer to Table 66 on page 157 ,
and for phase correct P W M refer to Table 67 on page 157 .
A change of the COM21:0 bits state will have effect at the first compare match after the bits are
written. For non-P W M modes, the action can be forced to have immediate effect by using the
FOC2 strobe bits.
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is
defined by the combination of the W aveform Generation mode ( W GM21:0) and Compare Output
mode (COM21:0) bits. The Compare Output mode bits do not affect the counting sequence,
while the W aveform Generation mode bits do. The COM21:0 bits control whether the P W M out-
put generated should be inverted or not (inverted or non-inverted P W M). For non-P W M modes
the COM21:0 bits control whether the output should be set, cleared, or toggled at a compare
match (See “Compare Match Output Unit” on page 148 ).
For detailed timing information refer to Figure 68 , Figure 69 , Figure 70 , and Figure 71 in
“Timer/Counter Timing Diagrams” on page 154 .
The simplest mode of operation is the normal mode ( W GM21:0 = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
149
2467X–AVR–06/11
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